148 Inspection Items for PCB Design - PCB checklist
1. data entry stage
whether the information received in the process is complete (including: schematic, *.brd file, bill of materials, pcb design instructions, pcb design or change requirements, standardization requirements, process design instructions)
2. confirm that the pcb template is up to date
3. confirm that the positioning device of the template is correct
4. whether the pcb design description, pcb design or change requirements, and standardization requirements are clear
5. confirm that the prohibited devices and wiring areas on the outline diagram have been reflected on the pcb template
6. compare the outline drawings and confirm that the dimensions and tolerances marked on the pcb are correct, and the metallized and non-metallized holes are accurately defined.
7. after confirming that the pcb template is accurate, it is best to lock the structural file to avoid misoperation and moving position. 2. inspection stage after layout a. device inspection
8. confirm whether all device packages are consistent with the company's unified library, whether the package library has been updated (check the running results with viewlog) if it is inconsistent, be sure to update symbols
9, motherboard and daughter board, single board and backplane, confirm that the signal corresponds, the position corresponds, the connector direction and silkscreen mark are correct, and the daughter board has anti-misinsertion measures, the device on the daughter board and the motherboard should not interfere 100, whether the components are 100% placed
11, open the place-bound of the device top and bottom layers to see if the drc caused by overlap is allowed
12, whether the mark point is sufficient and necessary
13, heavier components should be placed close to the pcb support point or support edge to reduce the warpage of the pcb
14, it is best to lock the structure-related devices after laying them out to prevent misoperation of the moving position
15, within 5mm around the crimping socket, the front is not allowed to have components with a height exceeding the height of the crimping socket. no components or solder joints are allowed on the back
16, confirm whether the device layout meets the process requirements (focus on bga, plcc, smd sockets)
17, components in metal housings, pay special attention not to contact other components, leave enough space
18, interface-related devices should be placed as close to the interface as possible, and the backplane bus driver should be placed as close to the backplane connector as possible
19, whether the chip device on the wave soldering surface has been converted to wave soldering package,
20, whether there are more than 50 manual solder joints 21, for axially inserting tall components on the pcb, horizontal mounting should be considered. leave room for lying down. and consider the fixing method, such as the fixed pad of the crystal oscillator 22, the device that needs to use the heat sink, confirm that there is sufficient spacing with other devices, and pay attention to the height of the main device within the heat sink b. function check 23, whether the digital circuit and analog circuit device layout of the digital analog hybrid board have been separated, whether the signal flow is reasonable24, and the a/d converter is placed across the analog-digital partition. 25, whether the layout of clock devices is reasonable26, whether the layout of high-speed signal devices is reasonable, 27, whether the termination devices have been reasonably placed (the source matching serial resistor should be placed at the driving end of the signal; the matching serial resistor in the middle is placed in the middle position; the terminal matching series resistor should be placed at the receiving end of the signal)28, whether the number and position of the decoupling capacitors of the ic device are reasonable29, the signal line takes the plane of different levels as the reference plane, and when crossing the plane division area, the reference plane is close to the trace area of the signal. 30. whether the layout of the protection circuit is reasonable and conducive to splitting 31, whether the fuse of the single-board power supply is placed near the connector and there is no circuit component in front 32, confirm that the strong signal and weak signal (power difference of 30db) circuits are arranged separately 33, whether the devices that may affect the emc experiment are placed according to the design guide or refer to successful experience. for example, the reset circuit of the panel should be slightly close to the reset button c. heat generation 34, heat-sensitive components (including liquid dielectric capacitors and crystal oscillators) should be kept away from high-power components, heat sinks and other heat sources as much as possible 35, whether the layout meets the thermal design requirements, the heat dissipation channel (executed according to the process design document) d. power supply 36, whether the ic power supply is too far away from the ic 37, whether the ldo and surrounding circuit layout is reasonable 38, whether the layout of surrounding circuits such as module power supply is reasonable 39, whether the overall layout of the power supply is reasonable e. whether the rules are set 40, whether all simulation constraints have been correctly added to the constraint manager 41, whether the physical and electrical rules are set correctly (pay attention to the constraint settings of the power supply network and ground network) 42, whether the spacing of the test via and test pin is sufficient 43, whether the thickness and scheme of the stackup meet the design and processing requirements 44, whether all differential line impedance with characteristic impedance requirements has been calculated, and use rules to control 3. check the stage after wiring e. digital analog 45, whether the traces of the digital circuit and the analog circuit are separated, whether the signal flow is reasonable46, a/d, d/a and similar circuits if the ground is divided, then does the signal line between the circuits go from the bridge point between the two places (except for the difference line)? 47. signal lines that must cross the gap between the split power supplies should refer to the complete ground plane. 48. if the formation design partition is not divided, ensure that the digital signal and analog signal are divided and routed. f. clock and high-speed part 49, is the impedance of the high-speed signal line consistent at each layer 50, is the high-speed differential signal line and similar signal line equal length, symmetrical, and parallel to the nearest parallel? 51. confirm that the clock line is on the inner layer as much as possible 52, confirm whether the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been routed according to the 3w principle as much as possible. 53. is there no fork test point on the clock, interrupt, reset signal, 100 gigabit/gigabit ethernet, and high-speed signal? 54. is 10h (h is the height of the signal line distance reference plane) between lvds and ttl/cmos signals as much as possible? 55. do clock lines and high-speed signal lines avoid traversing dense through-hole vias or device pin-to-pin traces? 56. whether the clock line has met the (si constraint) requirements (whether the clock signal trace has fewer holes, short traces, continuous reference plane, and the main reference plane is gnd as much as possible; if the gnd main reference plane layer is changed during layer change, it is a gnd via within 200 mil from the via (if the main reference plane of different levels is changed during layer change, is there a decoupling capacitor within the range of 200 mil from the via)? 57. do differential pairs, high-speed signal lines, and various types of bus meet the (si constraints) requirements g. emc and reliability 58, is there a layer of ground under the crystal oscillator? does the signal line pass between the device pins? for high-speed sensitive devices, does the signal line pass through the pins of the device? 59. there should be no sharp angles and right angles on the single-board signal trace (generally turning continuously at an angle of 135 degrees, and it is best to use arc-shaped or calculated cut copper foil for rf signal lines)60, for double-sided boards, check whether the high-speed signal line is wired next to its return ground wire; for multi-layer boards, check whether the high-speed signal line is as close to the ground plane trace as possible 61, for adjacent two-layer signal traces, try to trace vertically 62, avoid the signal line from the power module, common-mode inductor, transformer, filter 63, try to avoid the high-speed signal on the same layer of long-distance parallel trace 64, and whether there are shielded vias on the dividing edges of digital, analog and protected ground on the edge of the board? are multiple ground planes connected by vias? is the via distance less than 1/20 of the wavelength of the highest frequency signal? 65. is the signal trace corresponding to the surge suppression device short and thick on the surface? 66. confirm that there are no islands in the power supply and stratum, no excessive grooving, no long cracks in the ground plane caused by excessive or dense vias of the through-hole isolation disk, no slender strips and narrow channels 67, whether there are many ground vias (at least two ground planes are required) in the place where the signal line crosses more layers. 69. confirm that the power supply and ground energy can carry sufficient current. whether the number of vias meets the bearing requirements, (estimation method: 1a/mm line width when the outer layer copper thickness is 1oz, 0.5a/mm line width in the inner layer, and the short-term current is doubled)70, for power supplies with special requirements, whether the voltage drop requirements are met 71, in order to reduce the edge radiation effect of the plane, the 20h principle should be met as much as possible between the power supply layer and the stratum. (if possible, the more indentation of the power stack, the better). 72. if there is a land division, does the divided land not constitute a ring road? 73. do different power planes in adjacent layers avoid overlapping placement? 74. is the isolation of protected ground, -48v ground and gnd greater than 2mm? 75, is the -48v signal only -48v returning and not merging to other grounds? if you can't do it, please explain the reason in the remarks column. 76. is there a protective ground of 10~20mm near the panel with connectors, and the layers are connected with double rows of staggered holes? 77. is the distance between the power cord and other signal lines meet the safety requirements? i. no-cloth zone 78, under metal shell devices and heat dissipation devices, there should be no traces, copper skins and vias that may cause short circuits 79, around the mounting screws or washers should not cause short circuits such as traces, copper skins and vias 80, whether there are traces in the reserved position in the design requirements 81, the spacing between the off-line and copper foil of the inner layer of the non-metallized hole should be greater than 0.5mm (20mil), and the outer layer should be 0.3mm (12mil), the spacing between the inner layer of the veneer lifting wrench shaft hole and the copper foil should be greater than 2mm (80mil)82, the copper skin and wire to the edge of the board are recommended to be greater than 2mm, the minimum is 0.5mm 83, the inner layer of the copper sheet to the edge of the board is 1 ~ 2 mm, the minimum is 0.5mmj. pad outlet 84, for two pad mounted chip components (0805 and below packages), such as resistors, capacitors, the printed wire connected to its pad is best to be symmetrically led from the center position of the pad, and the printed line connected to the pad must have the same width, for the lead line with a line width of less than 0.3mm (12mil) can be ignored this regulation 85, the pad connected with the wider printed line, it is best to pass through a narrow printed line in the middle? (0805 and below packages)86, the line should be drawn from both ends of the pads of soic, plcc, qfp, sot, etc. as much as possible. silk screen printing 87, whether the device designation is missing, whether the position can correctly identify the device 88, whether the device designation meets the requirements of the company's standard 89, confirm the pin arrangement order of the device, the first pin mark, the polarity mark of the device, the correctness of the connector direction mark 90, whether the insertion board direction mark of the motherboard and the daughter board corresponds to 91. whether the backplane correctly marks the slot name, slot number, port name, and sheath direction 92, confirm whether the silkscreen printing required by the design is correct 93, confirm that the anti-static and rf board markings (used by rf boards) l. code/barcode 94, confirm that the pcb code is correct and comply with the company's specifications 95, confirm that the pcb coding position and level of the single board are correct (should be on the upper left of side a, silkscreen layer) 96, confirm that the pcb coding position and layer of the backplane are correct (should be on the upper right side of b) outer copper foil surface) 97, confirm that there is a barcode laser printing white screen printing marking area 98, confirm that there are no wires under the barcode frame and more than 0.5mm through holes 99, confirm that there can be no components with a height of more than 25mm within 20mm outside the barcode white screen printing area m. via 100, on the reflow soldering surface, the via cannot be designed on the pad. (the spacing between the vias and the pads of normal windowing should be greater than 0.5mm (20mil), and the spacing between the vias covered with green oil and the pads should be greater than 0.1 mm (4mil), method: open the same net drc, check the drc, and then close the same net drc)101, the arrangement of the vias should not be too dense to avoid large-scale fractures in the power supply and ground plane102, the hole diameter of the drilled vias should not be less than 1/10n. process 103, whether the device placement rate is 100% , whether the spread rate is 100% (if it does not reach 100%, it needs to be explained in the remarks) 104, whether the dangling line has been adjusted to the minimum, and the retained dangling line has been confirmed one by one; 105, whether the process problems feedback from the process department have been carefully checked o. large-area copper foil 106, for the large area of copper foil on the top and bottom, if there is no special need, the grid copper should be used [oblique mesh for veneer, orthogonal mesh for backplate, line width 0.3mm (12 mil), spacing 0.5mm (20mil)]107, the component pad in the large area of copper foil area should be designed as a flower pad to avoid false welding; when there is a current requirement, consider widening the ribs of the pad first, and then consider the full connection 108, when laying copper over a large area, you should try to avoid the appearance of dead copper (islands) without network connections 109, and pay attention to whether there are illegal connections and unreported drcp. test points 110, whether the test points of various power sources and grounds are sufficient (at least one test point per 2a current) 111, and confirm that the network without adding test points is confirmed to be streamlined112. confirm that test point 113 is not set on the plug-in that is not installed during production, whether the test via and test pin have been fixed (suitable for the test needle bed unchanged plate) q.drc 114, the spacing rule of test via and test pin should be set to the recommended distance first, check the drc, if there is still drc, then check drc 115 with the minimum distance setting, turn on the constraint set to open state, update the drc, check whether there are any unallowed errors 116 in drc, confirm that drc has been adjusted to the minimum, and confirm one by one if drc cannot be eliminated; r. optical positioning point 117, confirm that there is an optical positioning symbol on the pcb surface with mounted components 118, confirm that the optical positioning symbol is not pressed (silkscreen printing and copper foil trace) 119, the background of the optical positioning point must be the same, confirm that the whole board uses optical points to its center off-edge ≥ 5mm 120, confirm that the optical positioning reference symbol of the whole board has been assigned a coordinate value (it is recommended to place the optical positioning reference symbol in the form of a device), and it is an integer value in millimeters. 121, ics with a center distance of < 0.5 mm and bga devices with a center distance of less than 0.8 mm (31 mil) should be set up with optical anchor points near the diagonal of the component s. solder mask check 122, confirm whether there are special requirements for the type of pads are properly windowed (pay special attention to the design requirements of the hardware) 123, whether the via under the bga is treated as a cover oil plug hole 124, whether the via other than the test via has been opened with a small window or cover the oil plug hole 125, whether the windowing of the optical positioning point avoids exposed copper and exposed wire 126, whether there is a copper skin and properly opened the window for devices that require copper skin heat dissipation or ground shielding such as power chips and crystal oscillators. the device fixed by solder should have green oil to block the large-area diffusion of the solder 4. output processing documents t. drilling diagram 127, whether the pcb board thickness, number of layers, silk screen color, warpage, and other technical descriptions of notes are correct 128, whether the layer name, stacking order, media thickness, and copper foil thickness of the stacking diagram are correct; whether impedance control is required and whether the description is accurate. whether the layer name of the stack diagram is consistent with the name of its light drawing file 129, turn off the repeat code in the setting table, the drilling accuracy should be set to 2-5 130, whether the hole table and drilling file are the latest (when changing the hole, it must be regenerated)131, whether there is an abnormal hole diameter in the hole table, and whether the hole diameter of the crimping part is correct; whether the aperture tolerance is marked correctly 132, whether the vias of the fortress hole are listed separately and marked with "filled vias" u. light painting 133, the output of the light drawing file should be in rs274x format as much as possible, and the accuracy should be set to 5:5 134, art_aper.txt whether it is up to date (274x can be dispensed with)135, whether there is an abnormal report in the log file of the output light drawing file 136, and the edge and island of the negative layer are confirmed 137. use the light drawing inspection tool to check whether the light drawing file is consistent with the pcb (the revision should be compared with the comparison tool) 5. file set 138, pcb file: product model_specifications_single board code_version number.brd139, liner design file of the backplane: product model_specification_single board code_version number-cb[-t/b].brd140, pcb processing file: pcb coding .zip (including light drawing files of each layer, aperture table, drilling file and ncdrill.log; the panel also needs to have the panel file provided by the process *.dxf), and the backplane must also be attached to the liner file: pcb code-cb[-t/b].zip (including drill.art, *.drl, ncdrill.log)141, process design file: product model_specification_board code_version number-gy.doc142, smt coordinate file: product model_specification_veneer code_ version number -smt.txt, (when outputting the coordinate file, confirm that body center is selected, only if the origin of all smd libraries is the device center, symbol origin can be selected) 143, pcb structure file: product model_specifications_single board code_version number-mcad.zip (including the dxf and .emn files) 144, test files: product model_specifications_board code_version number-test.zip (including coordinate files of testprep.log and untest.lst or *.drl test points)145, archived drawing files: product model specifications - board name - version number .pdf, (including: cover, home page, silk screen printing of each layer, line of each layer, drilling diagram, backplate with liner diagram) 6. standardization 146, confirm the cover, the information on the home page is correct 147, confirm that the serial number of the drawing (corresponding to the sequence distribution of each layer of the pcb) is correct 148, and confirm that the pcb code on the drawing frame is correct
